1. Field of Invention
The present invention relates to the field of memory cells, and specifically to a single-poly memory cell fabricated in a standard CMOS process flow.
2. Description of Related Art
One of the recent developments in Electrically Erasable Programmable Read Only Memory (EEPROM) cells has been the use of a single polysilicon deposition process to form a link between a control capacitor, a tunneling capacitor and an EEPROM Field Effect Transistor (FET). Because there may be no direct electrical connections to the single-poly layer, it is referred to as a ‘floating gate’. The floating gate also forms the gate of the EEPROM FET. Before the use of a single poly layer, an EEPROM cell was typically constructed from two poly layers. One such dual-poly EEPROM cell 100a is illustrated in FIG. 1a. A goal of the dual-poly EEPROM cell is to tunnel electrons through the tunneling capacitor 102 onto the floating gate 112. By way of capacitive coupling, a voltage potential 110 is applied to the top plate connection 106 of the control capacitor 108 and this applied voltage is realized across the tunneling capacitor 102 and the FET gate capacitance 104. The applied potential will cause electrons, via Fowler-Nordheim (FN) tunneling, to tunnel through the tunneling capacitor 102 and onto the floating gate 112. Electrons are removed in a similar way but with an opposite applied potential across the tunneling capacitor 102.
FIG. 1b is a schematic drawing of the control capacitor 108, tunneling capacitor 102, and FET gate capacitor 104 drawn in the cross-section of FIG. 1a. In order for a significant amount of applied voltage to be distributed across the tunneling capacitor 102, the capacitance of the control capacitor 108 should be much larger than the sum of the tunneling capacitor 102 and FET gate capacitor 104. The output voltage across the tunneling capacitor is calculated as:
      V    FG    =                    C        C                              C          C                +                  C          T                +                  C          G                      ·          V      IN      When Cc>>(CT+CG) this simplifies to:
            V      FG        ≈                            C          C                          C          C                    ·              V        IN              =      V    IN  and essentially very little of the applied voltage is lost across the control capacitor 108.
A goal of single-poly memory cells is to operate in the same manner as a dual-poly EEPROM cell, but to lessen additional processing steps outside the process flow of standard CMOS processing. Thus far, however, this goal may not be completely realized. For example, FIG. 2 is a cross section of a typical single-poly EEPROM cell 200. The dual polysilicon stack is eliminated and a single poly layer 212 connects the tunneling 102, FET gate 104, and control 208 capacitors. In addition, the control capacitor 208 is constructed from an n+ well 214 and a thin oxide layer is grown on the well. In this example, the single-poly EEPROM cell 200 is easier to manufacture in standard CMOS processing because it may be manufactured with only one polysilicon deposition step and fewer overall fabrication steps. However, this particular single-poly EEPROM may not be completely manufacturable with a standard CMOS process flow in that it requires additional fabrication steps to support the oxide on top of the n+ diffusion 214 that forms part of the control capacitor 208.
In the above example, the n+ diffusion 214 provides contact to the bottom plate of the control capacitor and eliminates the voltage dependency of the control capacitor 208. Typically, the control capacitor oxide is grown from the n+ diffusion 214 to ensure quality oxide that provides good electrical insulation. That is, the control capacitor oxide does not easily allow charge stored on the single poly layer 212 to leak away. Given that it is desirable to have the control capacitance much larger than the capacitance of other capacitors connected to the single poly layer, the thickness of the oxide of the control capacitor is usually less than or equal to the thickness of the oxide of the tunneling or FET capacitor. The need for thin oxide grown on a heavily doped (n+) region implies additional processing that is beyond the scope of the standard CMOS process. Therefore, one object of the present application is to provide a single-poly memory device that is constructible in a standard CMOS processing flow.